From: bugzilla-daemon@libre-soc.org
To: libre-riscv-dev@lists.libre-riscv.org
Subject: [libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
Date: Sun, 10 May 2020 23:11:51 +0000
Message-ID: <bug-305-13-go6rvSnE2h@https.bugs.libre-soc.org/> (raw)
In-Reply-To: <bug-305-13@https.bugs.libre-soc.org/>
https://bugs.libre-soc.org/show_bug.cgi?id=305
--- Comment #31 from Luke Kenneth Casson Leighton <lkcl@lkcl.net> ---
these would be better (again) as (sigh) add(x,y) etc. sub(63, n) rather than
63-n
also if the use of EXTZ64 *really* is necessary, that's actually a bug in the
spec
rather than something that we should arbitrarily fix, and it should be
reported.
@@ -168,9 +168,9 @@
@inject()
def op_slw(self, RB, RS):
n = RB[59:64]
- r = ROTL32(RS[32:64], n)
+ r = ROTL32(EXTZ64(RS[32:64]), n.value)
if eq(RB[58], 0):
- m = MASK(32, 63 - n)
+ m = MASK(32, 63 - n.value)
else:
m = concat(0, repeat=64)
RA = r & m
--
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2020-05-08 15:17 [libre-riscv-dev] [Bug 305] New: " bugzilla-daemon
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