[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py

[bugzilla-daemon@libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=305

--- Comment #15 from Luke Kenneth Casson Leighton <lkcl@lkcl.net> ---
(In reply to Michael Nolan from comment #14)
> (In reply to Luke Kenneth Casson Leighton from comment #13)
> 
> > with "carry_in" being *generated* by ALUInputStage, ALUInputData should
> > *not* have "carry_in" as a field.
> 
> We still need a carry_in from XER for things like add with carry. 

ah doh, yes you are absolutely right.

hmm hmmm sooo....

actually.... the default action from the if elif batch is to copy that carry_in
from the input spec over to the output spec.


> 
> > the reason is because it will never be set by the *user* of this stage,
> > and consequently a dangling wire will end up being created.
> > -----
> > 
> > what's "so" intended for?
> 
> Summary Overflow.

okaay.  so if it's a generated output, set only as a result as part of the
operation (in the 2nd or 3rd stage), it should *not* be in the ispec(), only in
the ospec() for later stage(s)

basically:

* if something is needed in the stage it must be added to the ispec()

* if something is produced *by* the stage ot must be added to the ospec()

* if something is needed by later stages, the only way they will get it is by
"passing through" the current stage and consequently it has to be added to
*both* ispec and ospec.

* if a final output is generated by an early stage, then clearly the only way
to get it all the way to the ends is, again, by "passing through" to later
stages and consequently putting it into both ispec and ospec.

summary-out sounds like it is output-only (3rd stage?). 
 carry-out likewise (from 2nd stage)

carry-in you are right is needed as input *and* output on *this* (first) stage,
where in later stages it will not be.

a and b and op are all "passthru" for this 1st stage. however a and b are input
only or the 2nd stage, but you *might* need some of the information from op for
the 3rd stage.

welcome to pipelines :)

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