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From: bugzilla-daemon@libre-soc.org
To: libre-riscv-dev@lists.libre-riscv.org
Subject: [libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
Date: Tue, 19 May 2020 18:13:27 +0000
Message-ID: <bug-325-13-6FsIhMvxES@https.bugs.libre-soc.org/> (raw)
In-Reply-To: <bug-325-13@https.bugs.libre-soc.org/>

https://bugs.libre-soc.org/show_bug.cgi?id=325

--- Comment #5 from Luke Kenneth Casson Leighton <lkcl@lkcl.net> ---
(In reply to Jacob Lifshay from comment #4)
> I think this should also cover interrupts.
> 
> I would suggest having the execution unit be a FSM since traps/interrupts
> are rare, so the FSM is not activated unless a trap/interrupt is taken. When
> we receive an external interrupt, we could switch the decoder to insert a
> special trap instruction instead of decoding normally.

traps are stunningly simple, the only thing they do is change the MSR and NIA
(program counter).  and change SRR0 and SRR1. it is hardly even an FSM :)

i like the interrupt idea, i believe it is kinda expected to do this.

l.

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2020-05-19 12:28 [libre-riscv-dev] [Bug 325] New: " bugzilla-daemon
2020-05-19 12:29 ` [libre-riscv-dev] [Bug 325] " bugzilla-daemon
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