[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline

[bugzilla-daemon@libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=325

--- Comment #2 from Luke Kenneth Casson Leighton <lkcl@lkcl.net> ---
this code in microwatt execute1.vdhl tends to suggest that two SPRs need to be
outputted from TRAP:

* SRR0 (containing the PC *after* the trap is to return - NIA)
* SRR1 (containing the new MSR)

note they are also using a FSM, writing out the two registers SRR0 and SRR1
across
2 clock cycles.

    ctrl_tmp.irq_state <= WRITE_SRR0;
    exception := '0';
        illegal := '0';
        exception_nextpc := '0';
        v.e.exc_write_enable := '0';
        v.e.exc_write_reg := fast_spr_num(SPR_SRR0);
        v.e.exc_write_data := e_in.nia;

    if ctrl.irq_state = WRITE_SRR1 then
        v.e.exc_write_reg := fast_spr_num(SPR_SRR1);
        v.e.exc_write_data := ctrl.srr1;
            v.e.exc_write_enable := '1';
            ctrl_tmp.msr(MSR_SF) <= '1';
            ctrl_tmp.msr(MSR_EE) <= '0';
            ctrl_tmp.msr(MSR_PR) <= '0';
            ctrl_tmp.msr(MSR_IR) <= '0';
            ctrl_tmp.msr(MSR_DR) <= '0';
            ctrl_tmp.msr(MSR_RI) <= '0';
            ctrl_tmp.msr(MSR_LE) <= '1';
        f_out.redirect <= '1';
        f_out.redirect_nia <= ctrl.irq_nia;
        v.e.valid := e_in.valid;

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