[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline

[bugzilla-daemon@libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=325

--- Comment #17 from Luke Kenneth Casson Leighton <lkcl@lkcl.net> ---
Cole: example (A is to B, as C is to D).  examine case OP_TRAP and case OP_SC.

A:
                ctrl_tmp.irq_nia <= std_logic_vector(to_unsigned(16#C00#, 64));
                ctrl_tmp.srr1 <= msr_copy(ctrl.msr);

B:

                ????


C:
                    ctrl_tmp.irq_nia <= std_logic_vector(to_unsigned(16#700#,
64));
                    ctrl_tmp.srr1 <= msr_copy(ctrl.msr);

D:

                    comb += self.o.nia.data.eq(0x700)         # trap address
                    comb += self.o.nia.ok.eq(1)


it should be BLINDINGLY obvious that B should be:

                    comb += self.o.nia.data.eq(0xC00)         # trap address
                    comb += self.o.nia.ok.eq(1)


therefore, in switch statement OP_SC, that's what goes into that function.

and that's it.

ta-daaa.  OP_SC is completed.

wasn't that easy?

Q: do you understand or know what OP_SC is or does?
A: i don't... and don't care, and it is completely irrelevant to you, as well.

   (it's *optional* to have understanding: you may *desire* understanding,
    you may *like* to have understanding, but it is, fundamentally, *completely
    irrelevant* to the actual task)

Q: do we *need* to understand or know what OP_SC is or does?
A: no we do not.

Q: will it work?
A: yes it will.

Q: will there be bugs?
A: most probably, and those can be found with unit tests.

Q: do absolutely all the required unit tests have to be written *right now*?
A: no they do not.

Q: do we need to freeze and lock up solid in total fear at our total and
   complete lack of understanding just because those unit tests do not exist?
A: of course not.

so reading a 1300 page PDF is completely and utterly pointless.  and making
reading that 1300 page PDF a hard, fixed, absolute critical dependency on
*completing this task* is a false assumption, isn't it?

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