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From: bugzilla-daemon@libre-soc.org
To: libre-riscv-dev@lists.libre-riscv.org
Subject: [libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
Date: Fri, 05 Jun 2020 02:13:03 +0000
Message-ID: <bug-325-13-d1S5YIar7n@https.bugs.libre-soc.org/> (raw)
In-Reply-To: <bug-325-13@https.bugs.libre-soc.org/>

https://bugs.libre-soc.org/show_bug.cgi?id=325

--- Comment #41 from Luke Kenneth Casson Leighton <lkcl@lkcl.net> ---
https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/decoder/power_decoder2.py;hb=HEAD

for OP_SC, OP_RFID and OP_TRAP we need to set the fast spr fields in DecodeA,
DecodeB and so on, so that the fields are correctly set.

this may involve the CSV files, putting the information there.

example: OP_TRAP needs to output SRR0, therefore DecodeOut needs to set
fast_out to SRR0 when the opcode is OP_TRAP.

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2020-05-19 12:28 [libre-riscv-dev] [Bug 325] New: " bugzilla-daemon
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