[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline

[bugzilla-daemon@libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=325

--- Comment #32 from Luke Kenneth Casson Leighton <lkcl@lkcl.net> ---
-                # TODO translate this, import and use br_ext from branch stage
-                # f_out.redirect_nia <= a_in(63 downto 2) & "00"; -- srr0
+                comb += self.o.nia.data.eq(br_ext(a[63:1] & 0))
+                comb += self.o.nia.ok.eq(1)

br_ext already adds the 2 zeros.  & in vhdl means "concatenate".  however they
go MSB -> LSB order, python is LSB->MSB order

                comb += self.o.nia.data.eq(br_ext(a[2:]))

you removed all of these, please do put them back:

-        a_i, b_i, cia_i, msr_i = self.i.a, self.i.b, self.i.cia, self.i.msr
-        o, msr_o, nia_o = self.o.o, self.o.msr, self.o.nia
-        srr0_o, srr1_o = self.o.srr0, self.o.srr1
+        a_i, b_i = self.i.a, self.i.b


-                #     -- just update EE and RI
-                #     ctrl_tmp.msr(MSR_EE) <= c_in(MSR_EE);
-                #     ctrl_tmp.msr(MSR_RI) <= c_in(MSR_RI);
+                L = self.fields.FormX.L[0:-1]
+                with m.If(L):
+                    comb += self.o.msr[MSR_EE].eq(self.i.msr[MSR_EE])
+                    comb += self.o.msr[MSR_RI].eq(self.i.msr[MSR_RI])
+

here, this is copying the incoming MSR into the outgoing MSR.  that's
just wasting time.    look again: it says c_in, and we discussed that
this is to be moved in comment #28 to "a".

also, those defines MSR_xx do not exist.  note the comment at the top:
# TODO: turn these into python constants (just "MSR_SF = 63-0 # comment" etc.)
"""
    Listed in V3.0B Book III Chap 4.2.1
    -- MSR bit numbers
    constant MSR_SF  : integer := (63 - 0);     -- Sixty-Four bit mode
....
"""

i'm leaving it to you to create those constants.

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