From: Yehowshua <yimmanuel3@gatech.edu>
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: Re: [libre-riscv-dev] Minerva L1 Cache
Date: Mon, 15 Jun 2020 15:54:36 -0400
Message-ID: <077FCA11-14A9-4607-9833-BF7D50A93747@gatech.edu> (raw)
In-Reply-To: <CAPweEDztS0TrODPL7B53SK8XcF-NegpBYLW8TiKfhvqVq8yrWA@mail.gmail.com>
>
> with the current resources the scoreboard is not an immediate
> incremental priority: getting a functional core that executes
> instructions is a top priority... *and then* the scoreboard can be
> incrementally added to it if there is time to do so.
OK. So right now, it sounds like instructions execute in order with
scoreboard?
Are we simply stalling with instructional dependencies?
I’m assuming that right now there is no multi-issue or anything of that
nature at the moment?
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Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-15 2:41 Yehowshua
2020-06-15 3:02 ` Yehowshua
2020-06-15 4:32 ` Luke Kenneth Casson Leighton
2020-06-15 16:46 ` Yehowshua
2020-06-15 19:32 ` Luke Kenneth Casson Leighton
2020-06-15 19:54 ` Yehowshua [this message]
2020-06-15 20:10 ` Luke Kenneth Casson Leighton
2020-06-15 20:23 ` Yehowshua
2020-06-15 20:24 ` Yehowshua
2020-06-15 20:30 ` Yehowshua
2020-06-15 20:53 ` Luke Kenneth Casson Leighton
2020-06-15 21:08 ` Yehowshua
2020-06-15 21:54 ` Luke Kenneth Casson Leighton
2020-06-16 1:39 ` Cole Poirier
2020-06-16 1:53 ` Luke Kenneth Casson Leighton
2020-06-16 1:58 ` Cole Poirier
2020-06-15 22:19 ` Yehowshua
2020-06-16 0:03 ` Luke Kenneth Casson Leighton
2020-06-15 16:57 ` Yehowshua
2020-06-15 3:09 ` Yehowshua
2020-06-15 4:30 ` Luke Kenneth Casson Leighton
2020-06-15 3:24 ` Yehowshua
2020-06-15 4:04 ` Luke Kenneth Casson Leighton
2020-06-16 0:20 ` [libre-riscv-dev] L1 cache and GPU workloads Jacob Lifshay
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