From: Yehowshua <yimmanuel3@gatech.edu>
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: Re: [libre-riscv-dev] Minerva L1 Cache
Date: Mon, 15 Jun 2020 17:08:41 -0400
Message-ID: <36A521C7-583F-4562-8932-509898538E9B@gatech.edu> (raw)
In-Reply-To: <CAPweEDw5OVhVo=Z-OyDu-w=ON=URcSzBcs7wersJdpeBe_oBFw@mail.gmail.com>
>
> there *is* a test_cache.py already in that directory.
> (i'm currently making all imports explicit)
Right this is the formal.
The formal doesn’t make it clear how to actually
use the thing.
Another question: what is the interface you want to the cache?
I think you said you wanted to go with Minerva’s loadstore frontend?
Could be a bit tricky as the loadstore frontend uses stage specific
bit masks. Might be easier to morph the L1 cache to your needs directly.
From your video, it seems that there is no instruction cache vs. data cache.
Can you specify what interface you want to see from the cache’s perspective?
I suspect the only change we need to make is set s1_stall to Const(0), and disable
s2_addr in Minerva’s L1Cache.
Yehowshua
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Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-15 2:41 Yehowshua
2020-06-15 3:02 ` Yehowshua
2020-06-15 4:32 ` Luke Kenneth Casson Leighton
2020-06-15 16:46 ` Yehowshua
2020-06-15 19:32 ` Luke Kenneth Casson Leighton
2020-06-15 19:54 ` Yehowshua
2020-06-15 20:10 ` Luke Kenneth Casson Leighton
2020-06-15 20:23 ` Yehowshua
2020-06-15 20:24 ` Yehowshua
2020-06-15 20:30 ` Yehowshua
2020-06-15 20:53 ` Luke Kenneth Casson Leighton
2020-06-15 21:08 ` Yehowshua [this message]
2020-06-15 21:54 ` Luke Kenneth Casson Leighton
2020-06-16 1:39 ` Cole Poirier
2020-06-16 1:53 ` Luke Kenneth Casson Leighton
2020-06-16 1:58 ` Cole Poirier
2020-06-15 22:19 ` Yehowshua
2020-06-16 0:03 ` Luke Kenneth Casson Leighton
2020-06-15 16:57 ` Yehowshua
2020-06-15 3:09 ` Yehowshua
2020-06-15 4:30 ` Luke Kenneth Casson Leighton
2020-06-15 3:24 ` Yehowshua
2020-06-15 4:04 ` Luke Kenneth Casson Leighton
2020-06-16 0:20 ` [libre-riscv-dev] L1 cache and GPU workloads Jacob Lifshay
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