From: Yehowshua <yimmanuel3@gatech.edu>
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: Re: [libre-riscv-dev] Minerva L1 Cache
Date: Sun, 14 Jun 2020 23:09:36 -0400
Message-ID: <FD000400-6178-4570-836F-709FE3F468C0@gatech.edu> (raw)
In-Reply-To: <8A42B0DD-1009-49A4-AEB9-DBE04836FAAE@gatech.edu>
And more generally, if I understand things correctly:
Our memory architecture is the following?
cpu -> MMU -> L1 Cache -> main memory?
Yehowshua
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Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-15 2:41 Yehowshua
2020-06-15 3:02 ` Yehowshua
2020-06-15 4:32 ` Luke Kenneth Casson Leighton
2020-06-15 16:46 ` Yehowshua
2020-06-15 19:32 ` Luke Kenneth Casson Leighton
2020-06-15 19:54 ` Yehowshua
2020-06-15 20:10 ` Luke Kenneth Casson Leighton
2020-06-15 20:23 ` Yehowshua
2020-06-15 20:24 ` Yehowshua
2020-06-15 20:30 ` Yehowshua
2020-06-15 20:53 ` Luke Kenneth Casson Leighton
2020-06-15 21:08 ` Yehowshua
2020-06-15 21:54 ` Luke Kenneth Casson Leighton
2020-06-16 1:39 ` Cole Poirier
2020-06-16 1:53 ` Luke Kenneth Casson Leighton
2020-06-16 1:58 ` Cole Poirier
2020-06-15 22:19 ` Yehowshua
2020-06-16 0:03 ` Luke Kenneth Casson Leighton
2020-06-15 16:57 ` Yehowshua
2020-06-15 3:09 ` Yehowshua [this message]
2020-06-15 4:30 ` Luke Kenneth Casson Leighton
2020-06-15 3:24 ` Yehowshua
2020-06-15 4:04 ` Luke Kenneth Casson Leighton
2020-06-16 0:20 ` [libre-riscv-dev] L1 cache and GPU workloads Jacob Lifshay
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