From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: Re: [libre-riscv-dev] Minerva L1 Cache
Date: Mon, 15 Jun 2020 05:32:52 +0100
Message-ID: <CAPweEDwEQdkfJ+OiN4KTEr3SD8FhVQE0T0Z+1vJek_pi0W_etg@mail.gmail.com> (raw)
In-Reply-To: <909D7BCD-8ADB-438F-BCA7-44437DC92A99@gatech.edu>
On Monday, June 15, 2020, Yehowshua <yimmanuel3@gatech.edu> wrote:
>
> > I’m currently working on writing a Minerva like nMigen
> > cache that supports as many sets as desired - hopefully
> > we can use that.
>
> I need a cache with arbitrary amount of sets for my thesis
> anyways
ah ok now this makes sense.
> so - might be useful in a LibreSOC context too.
maybe. we will have to evaluate it. as i explained in the crossover
message there are other higher priority design requirements that are unique
and specially required for the design.
l.
--
---
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Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-15 2:41 Yehowshua
2020-06-15 3:02 ` Yehowshua
2020-06-15 4:32 ` Luke Kenneth Casson Leighton [this message]
2020-06-15 16:46 ` Yehowshua
2020-06-15 19:32 ` Luke Kenneth Casson Leighton
2020-06-15 19:54 ` Yehowshua
2020-06-15 20:10 ` Luke Kenneth Casson Leighton
2020-06-15 20:23 ` Yehowshua
2020-06-15 20:24 ` Yehowshua
2020-06-15 20:30 ` Yehowshua
2020-06-15 20:53 ` Luke Kenneth Casson Leighton
2020-06-15 21:08 ` Yehowshua
2020-06-15 21:54 ` Luke Kenneth Casson Leighton
2020-06-16 1:39 ` Cole Poirier
2020-06-16 1:53 ` Luke Kenneth Casson Leighton
2020-06-16 1:58 ` Cole Poirier
2020-06-15 22:19 ` Yehowshua
2020-06-16 0:03 ` Luke Kenneth Casson Leighton
2020-06-15 16:57 ` Yehowshua
2020-06-15 3:09 ` Yehowshua
2020-06-15 4:30 ` Luke Kenneth Casson Leighton
2020-06-15 3:24 ` Yehowshua
2020-06-15 4:04 ` Luke Kenneth Casson Leighton
2020-06-16 0:20 ` [libre-riscv-dev] L1 cache and GPU workloads Jacob Lifshay
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