From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: Re: [libre-riscv-dev] Minerva L1 Cache
Date: Mon, 15 Jun 2020 21:53:57 +0100
Message-ID: <CAPweEDw5OVhVo=Z-OyDu-w=ON=URcSzBcs7wersJdpeBe_oBFw@mail.gmail.com> (raw)
In-Reply-To: <7BA190FA-6551-4A23-BAAE-5CFC2B3838AE@gatech.edu>
On Mon, Jun 15, 2020 at 9:31 PM Yehowshua <yimmanuel3@gatech.edu> wrote:
>
> >
> > I reached out to Jean Paul from lambda concepts about this.
> > Once I figure out exactly how Minerva core works - I’ll write a
> > tiny unit bench for it. Hopefully this would be helpful in modifying
> > it for our needs.
yes please. please drop it into soc/src/soc/minerva/test/... ah!
excellent! there *is* a test_cache.py already in that directory.
(i'm currently making all imports explicit)
> Actually - I figured it out.
ah excellent
> Stage1 and stage2.
>
> Stage1 is address pre-fetch.
> Stage 2 is actual fetch.
okaay. which isn't documented. no code-comments (at all). sigh.
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Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-15 2:41 Yehowshua
2020-06-15 3:02 ` Yehowshua
2020-06-15 4:32 ` Luke Kenneth Casson Leighton
2020-06-15 16:46 ` Yehowshua
2020-06-15 19:32 ` Luke Kenneth Casson Leighton
2020-06-15 19:54 ` Yehowshua
2020-06-15 20:10 ` Luke Kenneth Casson Leighton
2020-06-15 20:23 ` Yehowshua
2020-06-15 20:24 ` Yehowshua
2020-06-15 20:30 ` Yehowshua
2020-06-15 20:53 ` Luke Kenneth Casson Leighton [this message]
2020-06-15 21:08 ` Yehowshua
2020-06-15 21:54 ` Luke Kenneth Casson Leighton
2020-06-16 1:39 ` Cole Poirier
2020-06-16 1:53 ` Luke Kenneth Casson Leighton
2020-06-16 1:58 ` Cole Poirier
2020-06-15 22:19 ` Yehowshua
2020-06-16 0:03 ` Luke Kenneth Casson Leighton
2020-06-15 16:57 ` Yehowshua
2020-06-15 3:09 ` Yehowshua
2020-06-15 4:30 ` Luke Kenneth Casson Leighton
2020-06-15 3:24 ` Yehowshua
2020-06-15 4:04 ` Luke Kenneth Casson Leighton
2020-06-16 0:20 ` [libre-riscv-dev] L1 cache and GPU workloads Jacob Lifshay
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