[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero - bugzilla-daemon

From: bugzilla-daemon@libre-soc.org
To: libre-riscv-dev@lists.libre-riscv.org
Subject: [libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero
Date: Thu, 21 May 2020 21:12:48 +0000
Message-ID: <bug-336-13-4esxRJC6gT@https.bugs.libre-soc.org/> (raw)
In-Reply-To: <bug-336-13@https.bugs.libre-soc.org/>

https://bugs.libre-soc.org/show_bug.cgi?id=336

--- Comment #2 from Cesar Strauss <cestrauss@gmail.com> ---
Dear Luke,

Please do not bother drawing a gate level diagram for the FSM. Your description
is enough.

For the dataflow (registers, ALU, muxes), yes, a diagram is useful, but do
represent the whole FSM as an empty box.

I find that I can better design an FSM by starting from a behavioral
description, preferably in the form of a timing diagram.

If you like, you can draw one in paper, of what you want to see in the GTKWave
window. With arrows linking what edge causes which transition in another
signal.

What do you think?

Regards,

Cesar

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