From: bugzilla-daemon@libre-soc.org
To: libre-riscv-dev@lists.libre-riscv.org
Subject: [libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero
Date: Sat, 23 May 2020 12:51:01 +0000
Message-ID: <bug-336-13-8tHfZvQhNM@https.bugs.libre-soc.org/> (raw)
In-Reply-To: <bug-336-13@https.bugs.libre-soc.org/>
https://bugs.libre-soc.org/show_bug.cgi?id=336
--- Comment #5 from Luke Kenneth Casson Leighton <lkcl@lkcl.net> ---
Cesar, hi,
just to let you know, this should *not* interfere with adding is_zero support.
it however will be necessary to use this:
if hasattr(self.oper_i, "zero_a"):
# ok now we know that this operation requires zero_a support, we can
# mux in zero_a. otherwise we must put register a straight through
i am doing a minor code-morph on MultiCompUnit which makes it suitable for
general use across multiple pipelines, as specified by "regspecs". an example
is below.
note that this example - which uses CompCROpSubset **NOT** CompALUOpSubset -
is why we will need the "detection" above.
please do not let this stop you from adding zero_a detection support, let us
keep in touch and coordinate here.
i will have to add "detect if there is an operand B immediate" in the same way,
so you can see how it is done.
class CompCROpSubset(Record):
def __init__(self, name=None):
layout = (('insn_type', InternalOp),
('fn_unit', Function),
('insn', 32),
('read_cr_whole', 1),
('write_cr_whole', 1),
)
class CRInputData(IntegerData):
regspec = [('INT', 'a', '0:63'), # 64 bit range
('INT', 'b', '0:63'), # 6B bit range
('CR', 'full_cr', '0:31'), # 32 bit range
('CR', 'cr_a', '0:3'), # 4 bit range
('CR', 'cr_b', '0:3'), # 4 bit range
('CR', 'cr_c', '0:3')] # 4 bit range
class CROutputData(IntegerData):
regspec = [('INT', 'o', '0:63'), # 64 bit range
('CR', 'full_cr', '0:31'), # 32 bit range
('CR', 'cr_o', '0:3')] # 4 bit range
...
class CRPipeSpec(CommonPipeSpec):
regspec = (CRInputData.regspec, CROutputData.regspec)
opsubsetkls = CompCROpSubset
--
You are receiving this mail because:
You are on the CC list for the bug.
_______________________________________________
libre-riscv-dev mailing list
libre-riscv-dev@lists.libre-riscv.org
http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev
next prev parent reply index
Thread overview: 66+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-21 16:24 [libre-riscv-dev] [Bug 336] New: add indicator to Decode2ExecuteType that RA is zero bugzilla-daemon
2020-05-21 16:35 ` [libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero bugzilla-daemon
2020-05-21 16:36 ` bugzilla-daemon
2020-05-21 21:12 ` bugzilla-daemon
2020-05-21 21:41 ` bugzilla-daemon
2020-05-22 1:11 ` bugzilla-daemon
2020-05-23 12:51 ` bugzilla-daemon [this message]
2020-05-23 13:07 ` bugzilla-daemon
2020-05-23 19:09 ` bugzilla-daemon
2020-05-23 19:16 ` bugzilla-daemon
2020-05-23 19:39 ` bugzilla-daemon
2020-05-23 20:52 ` bugzilla-daemon
2020-05-23 22:52 ` bugzilla-daemon
2020-05-23 23:10 ` bugzilla-daemon
2020-05-24 1:46 ` bugzilla-daemon
2020-05-24 3:33 ` bugzilla-daemon
2020-05-24 13:46 ` bugzilla-daemon
2020-05-24 14:00 ` bugzilla-daemon
2020-05-24 14:37 ` bugzilla-daemon
2020-05-24 14:44 ` bugzilla-daemon
2020-05-24 15:07 ` bugzilla-daemon
2020-05-24 20:01 ` bugzilla-daemon
2020-05-24 20:29 ` bugzilla-daemon
2020-05-24 20:41 ` bugzilla-daemon
2020-05-25 0:14 ` bugzilla-daemon
2020-05-25 0:56 ` bugzilla-daemon
2020-05-25 1:19 ` bugzilla-daemon
2020-05-25 1:27 ` bugzilla-daemon
2020-05-25 1:31 ` bugzilla-daemon
2020-05-25 2:21 ` bugzilla-daemon
2020-05-25 2:29 ` bugzilla-daemon
2020-05-25 4:05 ` bugzilla-daemon
2020-05-25 7:28 ` bugzilla-daemon
2020-05-25 9:42 ` bugzilla-daemon
2020-05-25 10:43 ` bugzilla-daemon
2020-05-25 15:14 ` bugzilla-daemon
2020-05-25 15:25 ` bugzilla-daemon
2020-05-25 15:32 ` bugzilla-daemon
2020-05-25 23:06 ` bugzilla-daemon
2020-05-25 23:41 ` bugzilla-daemon
2020-05-26 10:01 ` bugzilla-daemon
2020-05-26 10:15 ` bugzilla-daemon
2020-05-26 16:29 ` bugzilla-daemon
2020-05-26 17:22 ` bugzilla-daemon
2020-05-28 10:44 ` bugzilla-daemon
2020-05-31 16:42 ` bugzilla-daemon
2020-06-01 11:09 ` bugzilla-daemon
2020-06-01 11:46 ` bugzilla-daemon
2020-06-01 11:55 ` bugzilla-daemon
2020-06-01 12:01 ` bugzilla-daemon
2020-06-01 12:02 ` bugzilla-daemon
2020-06-01 21:50 ` bugzilla-daemon
2020-06-01 22:04 ` bugzilla-daemon
2020-06-02 23:06 ` bugzilla-daemon
2020-06-06 20:33 ` bugzilla-daemon
2020-06-06 20:53 ` bugzilla-daemon
2020-06-06 21:20 ` bugzilla-daemon
2020-06-06 22:38 ` bugzilla-daemon
2020-06-07 20:35 ` bugzilla-daemon
2020-06-07 22:55 ` bugzilla-daemon
2020-06-08 1:20 ` bugzilla-daemon
2020-06-08 1:28 ` bugzilla-daemon
2020-06-09 12:36 ` bugzilla-daemon
2020-06-09 12:43 ` bugzilla-daemon
2020-06-14 23:21 ` bugzilla-daemon
2020-06-14 23:42 ` bugzilla-daemon
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=bug-336-13-8tHfZvQhNM@https.bugs.libre-soc.org/ \
--to=bugzilla-daemon@libre-soc.org \
--cc=libre-riscv-dev@lists.libre-riscv.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Libre RISC-V Mailing list Archives (accessible via public-inbox)
Archives are clonable: git clone --mirror https://inbox.libre-soc.org/libre-riscv-dev
Example config snippet for mirrors
AGPL code for this site: git clone https://public-inbox.org/public-inbox.git