[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero

[bugzilla-daemon@libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=336

Luke Kenneth Casson Leighton <lkcl@lkcl.net> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
         Depends on|                            |334
            Summary|add indicator to            |ALU CompUnit needs to
                   |Decode2ExecuteType that RA  |recognise that RA (src1)
                   |is zero                     |can be zero

--- Comment #1 from Luke Kenneth Casson Leighton <lkcl@lkcl.net> ---
forgot that i had raised 334 last night.  this one can therefore be about the
CompUnit.

the change needed is:

* first that Decode2ExecuteType needs a flag ra_is_zero

* second that CompAluOpSubset and CompLogicalALUSubset need likewise

* third - and this is the kicker - that the FSM for src1_i needs a Mux to
select RA or zero *and* it needs to *no longer* request a READ for src1
(rd.req[0]) if the ra_is_zero flag is set.

* additionally that if the z flag is set, the rd_done part of the FSM does NOT
wait for GO_READ on the src1 port (rd.go[0])
i will draw out a diagram.

again.

:)


Referenced Bugs:

https://bugs.libre-soc.org/show_bug.cgi?id=334
[Bug 334] POWER decode A=zero needs to be set as a flag in Execute1Type
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