[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero

[bugzilla-daemon@libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=336

--- Comment #9 from Luke Kenneth Casson Leighton <lkcl@lkcl.net> ---
(In reply to Luke Kenneth Casson Leighton from comment #8)
> (In reply to Cesar Strauss from comment #7)
> > (In reply to Luke Kenneth Casson Leighton from comment #6)
> > > ok done for imm_data, here is the location, it is virtually a cookie-cut of
> > > what
> > > is done for imm_data, bear in mind it will need to be src_l.q[0] and because
> > > src_l.q[0] covers RA, where src_l.q[1] covers RB.  likewise the src1_or_imm
> > > needs to go into sl[0] not sl[1]
> > 
> > I have done the above.
> 
> excellent.
> 
> > I held my commit because you seemed to be working on the file.
> 
> yeh don't do that: just shove it in :)
> 
> > It's OK to commit now?
> 
> git pull to merge, first, then go for it.  i happen to just be going out
> shopping
> anyway.

looks great, cesar - unit test time.  it should be as simple as setting
dut.oper_i.zero_a.eq(1) - or adding an extra argument to op_sim() to
allow that to be set dynamically - then setting a to a non-zero value
and checking that, yes, actually, a is now irrelevant (set to zero).

a more advanced version of the op_sim() test should be not to set
rd.go.eq(0b11)
in an ad-hoc fashion: instead to check rd_rel_o bits.

this starts to be very much like the planned LD/ST unit test modifications,
and you could probably use the exact same code for both.

however please do everything in an incremental fashion: no more than 5-10/15
lines at a time when modifying existing code (if that is practical).

so, start with adding the extra argument to op_sim() to allow zero_a to be set

then add a test call in scoreboard_sim op_sim(a=12312313213, zero_a=True, ...)

and so on.

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