[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero

[bugzilla-daemon@libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=336

--- Comment #46 from Luke Kenneth Casson Leighton <lkcl@lkcl.net> ---
(In reply to Luke Kenneth Casson Leighton from comment #45)
> (In reply to Cesar Strauss from comment #43)
> 
> > So rdmask, as an input, must be driven and held high, for all the time that
> > busy_o is active?
> 
> yes - for now.  i will look into whether (and how, and if) it should be
> moved into CompXXXOpSubsets (into oper_i).

just fyi, Cesar:

https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/fu/alu/pipe_data.py;h=33f54b026b95e06860a9f8b6a9a1b2797fdd59ee;hb=93fb5e930101a3bbb317e6180fc598f56b43cb9c#l67

line 67 (right at the end).  there's a function, "rdflags", which is there for
all soc.fu.*.pipe_data.py and it will be called by the Decoder and passed the
data structure (Decode2Execute1Type) which has all of the information, from
the actual instruction, about which register file ports (rd.req[0-N]) should
be activated.

it has to be done from the Decoder because only the Decoder (PowerDecode2) has
the relevant information.

but... what PowerDecode2 *doesn't* know is the order of the regfile ports
at the Function Unit... so... the function "rdflags" defines it.

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