From: bugzilla-daemon@libre-soc.org
To: libre-riscv-dev@lists.libre-riscv.org
Subject: [libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero
Date: Tue, 26 May 2020 10:01:25 +0000
Message-ID: <bug-336-13-c4VXTTgL5p@https.bugs.libre-soc.org/> (raw)
In-Reply-To: <bug-336-13@https.bugs.libre-soc.org/>
https://bugs.libre-soc.org/show_bug.cgi?id=336
--- Comment #36 from Cesar Strauss <cestrauss@gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #35)
> it will be fascinating to compare against the formal proof
I saw src/soc/fu/compunits/formal/proof_fu.py. Very interesting.
How about a formal proof of the ALU interface?
Also, maybe DummyALU could be truly dummy (doesn't drive its signals), and let
Assume drive them, in the CompUnit formal proof.
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Thread overview: 66+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-21 16:24 [libre-riscv-dev] [Bug 336] New: add indicator to Decode2ExecuteType that RA is zero bugzilla-daemon
2020-05-21 16:35 ` [libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero bugzilla-daemon
2020-05-21 16:36 ` bugzilla-daemon
2020-05-21 21:12 ` bugzilla-daemon
2020-05-21 21:41 ` bugzilla-daemon
2020-05-22 1:11 ` bugzilla-daemon
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2020-05-26 10:01 ` bugzilla-daemon [this message]
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