[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero

[bugzilla-daemon@libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=336

--- Comment #17 from Luke Kenneth Casson Leighton <lkcl@lkcl.net> ---
(In reply to Luke Kenneth Casson Leighton from comment #16)

> sure.  i'd suggest doing this:
>      latchregister(m, self.get_out(i), data_r, req_l.q[i], name)
> -->
>      latchregister(m, self.get_out(i), data_r, req_l.q[i], name+"_l")

> sure - feel free to call it "oper_l" instead

btw, commit this immediately - do not wait to "accumulate" a series of commits,
and *definitely* do not put multiple separate and distinct "purposes" into
the one commit.

git is intelligent enough to merge commits that are not on the exact same line.
therefore, to speed up collaboration, do take advantage of that: do not wait,
just commit it - and commit "single-purpose".  if you find you want to use the
word "and" in the commit message, *stop* - it means that the commit is not
single-purpose.  more on that in HDL_workflow.

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