From: Lauri Kasanen <cand@gmx.com>
To: libre-riscv-dev@lists.libre-riscv.org
Subject: Re: [libre-riscv-dev] cache SRAM organisation
Date: Fri, 27 Mar 2020 12:03:26 +0200
Message-ID: <20200327120326.785de798331c48bb88b79ade@gmx.com> (raw)
In-Reply-To: <CAPweEDwf7s=r6bhq6N=VG7QQ1iD4jHYEG6mGvtxL32Uxnhzqwg@mail.gmail.com>
On Fri, 27 Mar 2020 09:44:30 +0000
Luke Kenneth Casson Leighton <lkcl@lkcl.net> wrote:
> when bypass latches are open and we run at 800mhz:
>
> * actual speed: 800 mhz
> * stages: 10 (double)
> * latency (completion time): 1.25e-9 times *10* = 1.25e-8 *HALF THE LATENCY*
Sorry, but isn't that double the latency?
- Lauri
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Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-24 22:32 Luke Kenneth Casson Leighton
2020-03-25 10:54 ` Staf Verhaegen
2020-03-25 12:33 ` Luke Kenneth Casson Leighton
2020-03-25 13:46 ` Staf Verhaegen
2020-03-25 15:53 ` Luke Kenneth Casson Leighton
2020-03-25 17:49 ` Jacob Lifshay
2020-03-26 12:18 ` Staf Verhaegen
2020-03-26 12:31 ` Staf Verhaegen
2020-03-26 15:15 ` Luke Kenneth Casson Leighton
2020-03-26 15:15 ` Luke Kenneth Casson Leighton
2020-03-26 20:08 ` Staf Verhaegen
2020-03-26 21:28 ` Luke Kenneth Casson Leighton
2020-03-27 9:08 ` Staf Verhaegen
2020-03-27 9:16 ` Luke Kenneth Casson Leighton
2020-03-27 9:40 ` Staf Verhaegen
2020-03-27 9:46 ` Luke Kenneth Casson Leighton
2020-03-27 9:52 ` Luke Kenneth Casson Leighton
2020-03-26 12:27 ` Staf Verhaegen
2020-03-26 13:05 ` Luke Kenneth Casson Leighton
2020-03-26 20:18 ` Staf Verhaegen
2020-03-26 21:37 ` Luke Kenneth Casson Leighton
2020-03-27 9:25 ` Staf Verhaegen
2020-03-27 9:44 ` Luke Kenneth Casson Leighton
2020-03-27 10:03 ` Lauri Kasanen [this message]
2020-03-27 10:10 ` Luke Kenneth Casson Leighton
2020-03-27 10:36 ` Staf Verhaegen
2020-03-27 10:59 ` Luke Kenneth Casson Leighton
2020-03-28 14:08 ` [libre-riscv-dev] Clock Gating (was cache SRAM organisation) Staf Verhaegen
2020-03-28 14:26 ` Luke Kenneth Casson Leighton
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