From: Staf Verhaegen <staf@fibraservi.eu>
To: libre-riscv-dev@lists.libre-riscv.org
Subject: Re: [libre-riscv-dev] cache SRAM organisation
Date: Fri, 27 Mar 2020 11:36:15 +0100
Message-ID: <9e44930a0332eff507661e617796b9d0674b0e05.camel@fibraservi.eu> (raw)
In-Reply-To: <CAPweEDwf7s=r6bhq6N=VG7QQ1iD4jHYEG6mGvtxL32Uxnhzqwg@mail.gmail.com>
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Luke Kenneth Casson Leighton schreef op vr 27-03-2020 om 09:44 [+0000]:
> On Fri, Mar 27, 2020 at 9:25 AM Staf Verhaegen <staf@fibraservi.eu> wrote:
> > My point is that you will have the same performance for the fixed 5-stage pipeline running @ 800MHz
>
> no, it won't: it'll be half the clock speed. it won't be double thenumber of computations: it'll be the exact same number ofcomputations. therefore, half the speed means half the number ofcomputations because the *throughput* is the same
> when you use "cpufreq-set" to change the clock rate, if the clock rateis halved, the computer is twice as slow.
You are right.
> yes it's confusing :)
Yes and no, it is the basic functionality of a pipeline :(
You have the same latency but can have double the number of operations in flight.
greets,
Staf.
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Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-24 22:32 Luke Kenneth Casson Leighton
2020-03-25 10:54 ` Staf Verhaegen
2020-03-25 12:33 ` Luke Kenneth Casson Leighton
2020-03-25 13:46 ` Staf Verhaegen
2020-03-25 15:53 ` Luke Kenneth Casson Leighton
2020-03-25 17:49 ` Jacob Lifshay
2020-03-26 12:18 ` Staf Verhaegen
2020-03-26 12:31 ` Staf Verhaegen
2020-03-26 15:15 ` Luke Kenneth Casson Leighton
2020-03-26 15:15 ` Luke Kenneth Casson Leighton
2020-03-26 20:08 ` Staf Verhaegen
2020-03-26 21:28 ` Luke Kenneth Casson Leighton
2020-03-27 9:08 ` Staf Verhaegen
2020-03-27 9:16 ` Luke Kenneth Casson Leighton
2020-03-27 9:40 ` Staf Verhaegen
2020-03-27 9:46 ` Luke Kenneth Casson Leighton
2020-03-27 9:52 ` Luke Kenneth Casson Leighton
2020-03-26 12:27 ` Staf Verhaegen
2020-03-26 13:05 ` Luke Kenneth Casson Leighton
2020-03-26 20:18 ` Staf Verhaegen
2020-03-26 21:37 ` Luke Kenneth Casson Leighton
2020-03-27 9:25 ` Staf Verhaegen
2020-03-27 9:44 ` Luke Kenneth Casson Leighton
2020-03-27 10:03 ` Lauri Kasanen
2020-03-27 10:10 ` Luke Kenneth Casson Leighton
2020-03-27 10:36 ` Staf Verhaegen [this message]
2020-03-27 10:59 ` Luke Kenneth Casson Leighton
2020-03-28 14:08 ` [libre-riscv-dev] Clock Gating (was cache SRAM organisation) Staf Verhaegen
2020-03-28 14:26 ` Luke Kenneth Casson Leighton
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