From: Staf Verhaegen <staf@fibraservi.eu>
To: libre-riscv-dev@lists.libre-riscv.org
Subject: Re: [libre-riscv-dev] cache SRAM organisation
Date: Fri, 27 Mar 2020 10:40:50 +0100
Message-ID: <b26f79a2b7dd14ba4ad19240ec9986630f1085ff.camel@fibraservi.eu> (raw)
In-Reply-To: <CAPweEDxeyMEQJP_Dwh0TATbPh_gLPa8yiYdj-42yG0xKuQsUxA@mail.gmail.com>
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Luke Kenneth Casson Leighton schreef op vr 27-03-2020 om 09:16 [+0000]:
> On Fri, Mar 27, 2020 at 9:09 AM Staf Verhaegen <staf@fibraservi.eu> wrote:
> > I still feel you intermix synchronous and write-through in this statement, the above seems to be possible with synchronous SRAMs.
>
> this would be good. what would help clarify immensely is if you couldlet us know what options to nmigen Memory class are "supported".then it is really clear.
The nmigen Memory abstraction does not seem to allow a good representation of a write-through SRAM. AFAICS it does not allow to have the output of the read port be changed by what you write on the write port.
greets,
Staf.
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Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-24 22:32 Luke Kenneth Casson Leighton
2020-03-25 10:54 ` Staf Verhaegen
2020-03-25 12:33 ` Luke Kenneth Casson Leighton
2020-03-25 13:46 ` Staf Verhaegen
2020-03-25 15:53 ` Luke Kenneth Casson Leighton
2020-03-25 17:49 ` Jacob Lifshay
2020-03-26 12:18 ` Staf Verhaegen
2020-03-26 12:31 ` Staf Verhaegen
2020-03-26 15:15 ` Luke Kenneth Casson Leighton
2020-03-26 15:15 ` Luke Kenneth Casson Leighton
2020-03-26 20:08 ` Staf Verhaegen
2020-03-26 21:28 ` Luke Kenneth Casson Leighton
2020-03-27 9:08 ` Staf Verhaegen
2020-03-27 9:16 ` Luke Kenneth Casson Leighton
2020-03-27 9:40 ` Staf Verhaegen [this message]
2020-03-27 9:46 ` Luke Kenneth Casson Leighton
2020-03-27 9:52 ` Luke Kenneth Casson Leighton
2020-03-26 12:27 ` Staf Verhaegen
2020-03-26 13:05 ` Luke Kenneth Casson Leighton
2020-03-26 20:18 ` Staf Verhaegen
2020-03-26 21:37 ` Luke Kenneth Casson Leighton
2020-03-27 9:25 ` Staf Verhaegen
2020-03-27 9:44 ` Luke Kenneth Casson Leighton
2020-03-27 10:03 ` Lauri Kasanen
2020-03-27 10:10 ` Luke Kenneth Casson Leighton
2020-03-27 10:36 ` Staf Verhaegen
2020-03-27 10:59 ` Luke Kenneth Casson Leighton
2020-03-28 14:08 ` [libre-riscv-dev] Clock Gating (was cache SRAM organisation) Staf Verhaegen
2020-03-28 14:26 ` Luke Kenneth Casson Leighton
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