From: Staf Verhaegen <staf@fibraservi.eu>
To: libre-riscv-dev@lists.libre-riscv.org
Subject: Re: [libre-riscv-dev] cache SRAM organisation
Date: Fri, 27 Mar 2020 10:08:48 +0100
Message-ID: <65e762e270e3660044604cc48f4fbd554d34af13.camel@fibraservi.eu> (raw)
In-Reply-To: <CAPweEDx9YH=0DWviRYJySR9++n-Nd88ZHkRb8EkWhah3x4MbeQ@mail.gmail.com>
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Luke Kenneth Casson Leighton schreef op do 26-03-2020 om 21:28 [+0000]:
> On Thu, Mar 26, 2020 at 8:08 PM Staf Verhaegen <staf@fibraservi.eu> wrote:
> > Luke Kenneth Casson Leighton schreef op do 26-03-2020 om 15:15 [+0000]:
> > > On Thursday, March 26, 2020, Staf Verhaegen <staf@fibraservi.eu> wrote:
> > > > I can understand you do this to implement functional units withconfigurable pipeline length but I would strongly discourage to pipelineregister files after each other .
> > >
> > >
> > > "pipeline register files after each other"? apologies i am not clear whatyou mean, here. do you mean "don't do write-thru on the Regfile"?
> >
> > No I meant for example connecting the output of one port of an asynchronous RAM to for example the address input of another port of an asynchronous RAM.
>
> ah right, no definitely not. the connections are:
> RegisterFile readport[0..R] ==> FunctionUnit[0..M] operand latches pipeline stage 0 pipeline stage 1 ... pipeline stage NRegisterFile writeport[0..W] <== FunctionUnit[0..M] result latches
> (and also: )register file bypass forwardingbus <== FunctionUnit result latchesregister file bypass forwardingbus ==> FunctionUnit operand latches
> so the asynchronous SRAMs will definitely *only* be connected to SFFlatches. *not* to other asynchronous SRAMs.
I still feel you intermix synchronous and write-through in this statement, the above seems to be possible with synchronous SRAMs.
greets,
Staf.
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Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-24 22:32 Luke Kenneth Casson Leighton
2020-03-25 10:54 ` Staf Verhaegen
2020-03-25 12:33 ` Luke Kenneth Casson Leighton
2020-03-25 13:46 ` Staf Verhaegen
2020-03-25 15:53 ` Luke Kenneth Casson Leighton
2020-03-25 17:49 ` Jacob Lifshay
2020-03-26 12:18 ` Staf Verhaegen
2020-03-26 12:31 ` Staf Verhaegen
2020-03-26 15:15 ` Luke Kenneth Casson Leighton
2020-03-26 15:15 ` Luke Kenneth Casson Leighton
2020-03-26 20:08 ` Staf Verhaegen
2020-03-26 21:28 ` Luke Kenneth Casson Leighton
2020-03-27 9:08 ` Staf Verhaegen [this message]
2020-03-27 9:16 ` Luke Kenneth Casson Leighton
2020-03-27 9:40 ` Staf Verhaegen
2020-03-27 9:46 ` Luke Kenneth Casson Leighton
2020-03-27 9:52 ` Luke Kenneth Casson Leighton
2020-03-26 12:27 ` Staf Verhaegen
2020-03-26 13:05 ` Luke Kenneth Casson Leighton
2020-03-26 20:18 ` Staf Verhaegen
2020-03-26 21:37 ` Luke Kenneth Casson Leighton
2020-03-27 9:25 ` Staf Verhaegen
2020-03-27 9:44 ` Luke Kenneth Casson Leighton
2020-03-27 10:03 ` Lauri Kasanen
2020-03-27 10:10 ` Luke Kenneth Casson Leighton
2020-03-27 10:36 ` Staf Verhaegen
2020-03-27 10:59 ` Luke Kenneth Casson Leighton
2020-03-28 14:08 ` [libre-riscv-dev] Clock Gating (was cache SRAM organisation) Staf Verhaegen
2020-03-28 14:26 ` Luke Kenneth Casson Leighton
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