From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: Re: [libre-riscv-dev] cache SRAM organisation
Date: Fri, 27 Mar 2020 09:52:22 +0000
Message-ID: <CAPweEDyKDXky1GPUNnhgR6i=ko4epmZUFL=jB9KvA9ok50JhZg@mail.gmail.com> (raw)
In-Reply-To: <CAPweEDzvKyPZTGsW53K1RqoOf6N4nxFywBf8gK372M=h00Ctzg@mail.gmail.com>
On Fri, Mar 27, 2020 at 9:46 AM Luke Kenneth Casson Leighton
<lkcl@lkcl.net> wrote:
>
> On Fri, Mar 27, 2020 at 9:40 AM Staf Verhaegen <staf@fibraservi.eu> wrote:
> > The nmigen Memory abstraction does not seem to allow a good representation of a write-through SRAM. AFAICS it does not allow to have the output of the read port be changed by what you write on the write port.
>
> urk, that's an important oversight. we'll need to raise a bugreport
> with whitequark about it.
ok raised a bugreport here.
if nothing else, Staf, we just augment the SRAM with external MUX
logic, or we simply use SFFs for the RegFile. it'll be big, but it
will work.
l.
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Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-24 22:32 Luke Kenneth Casson Leighton
2020-03-25 10:54 ` Staf Verhaegen
2020-03-25 12:33 ` Luke Kenneth Casson Leighton
2020-03-25 13:46 ` Staf Verhaegen
2020-03-25 15:53 ` Luke Kenneth Casson Leighton
2020-03-25 17:49 ` Jacob Lifshay
2020-03-26 12:18 ` Staf Verhaegen
2020-03-26 12:31 ` Staf Verhaegen
2020-03-26 15:15 ` Luke Kenneth Casson Leighton
2020-03-26 15:15 ` Luke Kenneth Casson Leighton
2020-03-26 20:08 ` Staf Verhaegen
2020-03-26 21:28 ` Luke Kenneth Casson Leighton
2020-03-27 9:08 ` Staf Verhaegen
2020-03-27 9:16 ` Luke Kenneth Casson Leighton
2020-03-27 9:40 ` Staf Verhaegen
2020-03-27 9:46 ` Luke Kenneth Casson Leighton
2020-03-27 9:52 ` Luke Kenneth Casson Leighton [this message]
2020-03-26 12:27 ` Staf Verhaegen
2020-03-26 13:05 ` Luke Kenneth Casson Leighton
2020-03-26 20:18 ` Staf Verhaegen
2020-03-26 21:37 ` Luke Kenneth Casson Leighton
2020-03-27 9:25 ` Staf Verhaegen
2020-03-27 9:44 ` Luke Kenneth Casson Leighton
2020-03-27 10:03 ` Lauri Kasanen
2020-03-27 10:10 ` Luke Kenneth Casson Leighton
2020-03-27 10:36 ` Staf Verhaegen
2020-03-27 10:59 ` Luke Kenneth Casson Leighton
2020-03-28 14:08 ` [libre-riscv-dev] Clock Gating (was cache SRAM organisation) Staf Verhaegen
2020-03-28 14:26 ` Luke Kenneth Casson Leighton
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