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From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: Re: [libre-riscv-dev] Clock Gating (was cache SRAM organisation)
Date: Sat, 28 Mar 2020 14:26:09 +0000
Message-ID: <CAPweEDxhPBNgT2sPs1b9KAfq9oBmtcGkgp=UboV3d0VoiOXoHA@mail.gmail.com> (raw)
In-Reply-To: <0d35e45bd81eeaecedeb64dc5061c1e33c89630c.camel@fibraservi.eu>

On Sat, Mar 28, 2020 at 2:08 PM Staf Verhaegen <staf@fibraservi.eu> wrote:

> There is an (IMO better) alternative for what you are doing with your pass-through registers and that is clock gating (wikipedia, allaboutcircuits).

ok that's very valuable and appreciated.  will reply here
http://bugs.libre-riscv.org/show_bug.cgi?id=270

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Thread overview: 29+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-03-24 22:32 [libre-riscv-dev] cache SRAM organisation Luke Kenneth Casson Leighton
2020-03-25 10:54 ` Staf Verhaegen
2020-03-25 12:33   ` Luke Kenneth Casson Leighton
2020-03-25 13:46     ` Staf Verhaegen
2020-03-25 15:53       ` Luke Kenneth Casson Leighton
2020-03-25 17:49         ` Jacob Lifshay
2020-03-26 12:18         ` Staf Verhaegen
2020-03-26 12:31           ` Staf Verhaegen
2020-03-26 15:15             ` Luke Kenneth Casson Leighton
2020-03-26 15:15           ` Luke Kenneth Casson Leighton
2020-03-26 20:08             ` Staf Verhaegen
2020-03-26 21:28               ` Luke Kenneth Casson Leighton
2020-03-27  9:08                 ` Staf Verhaegen
2020-03-27  9:16                   ` Luke Kenneth Casson Leighton
2020-03-27  9:40                     ` Staf Verhaegen
2020-03-27  9:46                       ` Luke Kenneth Casson Leighton
2020-03-27  9:52                         ` Luke Kenneth Casson Leighton
2020-03-26 12:27         ` Staf Verhaegen
2020-03-26 13:05           ` Luke Kenneth Casson Leighton
2020-03-26 20:18             ` Staf Verhaegen
2020-03-26 21:37               ` Luke Kenneth Casson Leighton
2020-03-27  9:25                 ` Staf Verhaegen
2020-03-27  9:44                   ` Luke Kenneth Casson Leighton
2020-03-27 10:03                     ` Lauri Kasanen
2020-03-27 10:10                       ` Luke Kenneth Casson Leighton
2020-03-27 10:36                     ` Staf Verhaegen
2020-03-27 10:59                       ` Luke Kenneth Casson Leighton
2020-03-28 14:08                         ` [libre-riscv-dev] Clock Gating (was cache SRAM organisation) Staf Verhaegen
2020-03-28 14:26                           ` Luke Kenneth Casson Leighton [this message]

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