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From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
To: Staf Verhaegen <staf@fibraservi.eu>,
	 Libre-RISCV General Development
	<libre-riscv-dev@lists.libre-riscv.org>
Subject: [libre-riscv-dev] cache SRAM organisation
Date: Tue, 24 Mar 2020 22:32:52 +0000
Message-ID: <CAPweEDx5QCCKxSr1gfuyuw_2D68Ld8fK85bEmmMTZi8S3w2E9g@mail.gmail.com> (raw)

https://groups.google.com/d/msg/comp.arch/cbGAlcCjiZE/mgMZVINVIAAJ

Staf can i ask you the favour of reviewing Mitch's comments about cache
design?

in particular the comments about the possibility of using multiported SRAM
cells as long as only 1R or 1W is done on any given cell?

also something about doing the FFs yourself, close to the SRAM cells?

l.



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Thread overview: 29+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-03-24 22:32 Luke Kenneth Casson Leighton [this message]
2020-03-25 10:54 ` Staf Verhaegen
2020-03-25 12:33   ` Luke Kenneth Casson Leighton
2020-03-25 13:46     ` Staf Verhaegen
2020-03-25 15:53       ` Luke Kenneth Casson Leighton
2020-03-25 17:49         ` Jacob Lifshay
2020-03-26 12:18         ` Staf Verhaegen
2020-03-26 12:31           ` Staf Verhaegen
2020-03-26 15:15             ` Luke Kenneth Casson Leighton
2020-03-26 15:15           ` Luke Kenneth Casson Leighton
2020-03-26 20:08             ` Staf Verhaegen
2020-03-26 21:28               ` Luke Kenneth Casson Leighton
2020-03-27  9:08                 ` Staf Verhaegen
2020-03-27  9:16                   ` Luke Kenneth Casson Leighton
2020-03-27  9:40                     ` Staf Verhaegen
2020-03-27  9:46                       ` Luke Kenneth Casson Leighton
2020-03-27  9:52                         ` Luke Kenneth Casson Leighton
2020-03-26 12:27         ` Staf Verhaegen
2020-03-26 13:05           ` Luke Kenneth Casson Leighton
2020-03-26 20:18             ` Staf Verhaegen
2020-03-26 21:37               ` Luke Kenneth Casson Leighton
2020-03-27  9:25                 ` Staf Verhaegen
2020-03-27  9:44                   ` Luke Kenneth Casson Leighton
2020-03-27 10:03                     ` Lauri Kasanen
2020-03-27 10:10                       ` Luke Kenneth Casson Leighton
2020-03-27 10:36                     ` Staf Verhaegen
2020-03-27 10:59                       ` Luke Kenneth Casson Leighton
2020-03-28 14:08                         ` [libre-riscv-dev] Clock Gating (was cache SRAM organisation) Staf Verhaegen
2020-03-28 14:26                           ` Luke Kenneth Casson Leighton

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