From: Staf Verhaegen <staf@fibraservi.eu>
To: libre-riscv-dev@lists.libre-riscv.org
Subject: Re: [libre-riscv-dev] cache SRAM organisation
Date: Thu, 26 Mar 2020 13:31:38 +0100
Message-ID: <350514fc6cf0b578804b85775beb8c0e039cab1e.camel@fibraservi.eu> (raw)
In-Reply-To: <db557324bcb76a999d8f66c75b9319974a1a1e08.camel@fibraservi.eu>
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(Sorry send to early)
> .In theory on a single port SRAM
In theory on a single port SRAM the write data input and the Q data output could be on opposite sides of the block but I will make sure that these pins are on the same side of the block and close together so you don't need much wire to connect a pass-through MUX.
greets,
Staf.
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Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-24 22:32 Luke Kenneth Casson Leighton
2020-03-25 10:54 ` Staf Verhaegen
2020-03-25 12:33 ` Luke Kenneth Casson Leighton
2020-03-25 13:46 ` Staf Verhaegen
2020-03-25 15:53 ` Luke Kenneth Casson Leighton
2020-03-25 17:49 ` Jacob Lifshay
2020-03-26 12:18 ` Staf Verhaegen
2020-03-26 12:31 ` Staf Verhaegen [this message]
2020-03-26 15:15 ` Luke Kenneth Casson Leighton
2020-03-26 15:15 ` Luke Kenneth Casson Leighton
2020-03-26 20:08 ` Staf Verhaegen
2020-03-26 21:28 ` Luke Kenneth Casson Leighton
2020-03-27 9:08 ` Staf Verhaegen
2020-03-27 9:16 ` Luke Kenneth Casson Leighton
2020-03-27 9:40 ` Staf Verhaegen
2020-03-27 9:46 ` Luke Kenneth Casson Leighton
2020-03-27 9:52 ` Luke Kenneth Casson Leighton
2020-03-26 12:27 ` Staf Verhaegen
2020-03-26 13:05 ` Luke Kenneth Casson Leighton
2020-03-26 20:18 ` Staf Verhaegen
2020-03-26 21:37 ` Luke Kenneth Casson Leighton
2020-03-27 9:25 ` Staf Verhaegen
2020-03-27 9:44 ` Luke Kenneth Casson Leighton
2020-03-27 10:03 ` Lauri Kasanen
2020-03-27 10:10 ` Luke Kenneth Casson Leighton
2020-03-27 10:36 ` Staf Verhaegen
2020-03-27 10:59 ` Luke Kenneth Casson Leighton
2020-03-28 14:08 ` [libre-riscv-dev] Clock Gating (was cache SRAM organisation) Staf Verhaegen
2020-03-28 14:26 ` Luke Kenneth Casson Leighton
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