[libre-riscv-dev] Understanding the LibreSOC core

[libre-riscv-dev] Understanding the LibreSOC core

[Sanjay Menon]

Hi,

Currently making a little progress on the nMigen tool.

Got to see some interesting things been discussed on the Alexa IOT pitch
for LibreSOC.

I have a few questions for you guys

1.Where do I start if I where to check into the LibreSoC source code?

2. Is this SoC in any way similar to the Xilinx ZYNQ architecture?.
Where the ARM embedded processor would be replaced by PowerPC and the
reconfigurable logic is converted to a GPU like entity, together forming a
heterogeneous SoC.

3. Do you plan to run the SoC on an FPGA for prototyping and testing
purposes?, or are you using some other methodologies?

Thanks and regards,
Sanjay
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Re: [libre-riscv-dev] Understanding the LibreSOC core

[Luke Kenneth Casson Leighton]

On Mon, Jun 8, 2020 at 7:03 PM Sanjay Menon <sanjayamenon.mec@gmail.com> wrote:
>
> Hi,

hi! :)

> Currently making a little progress on the nMigen tool.

excellent. you understand gates (and verilog) already, so it should be
pretty straightforward.  Cesar i think got used to nmigen in around,
maybe 2 weeks?  it took me about that long.

> Got to see some interesting things been discussed on the Alexa IOT pitch
> for LibreSOC.
>
> I have a few questions for you guys
>
> 1.Where do I start if I were to check into the LibreSoC source code?

ha, ok, hum, bear in mind it's 75,000 lines, ok?  so i do recommend:
be patient, both with us and with yourself.  you've got nmigen already
(and yosys? and symbiyosys? - you only need symbiyosys and its
dependencies if running the formal proof tests)

have you followed the "quick peek at the code" on the frontpage?
https://libre-soc.org/ if so, you have the 3 key repositories, and you
could, for example, run the simple_core.py test that i posted about,
yesterday.  you *may* need to re-run pywriter.py though - see the
top-level Makefile

you can also just browse the source code directly online.  here's
core.py for example:
https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/simple/core.py;hb=HEAD

and its unit test:
https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/simple/test/test_core.py;hb=HEAD

if you use vim, i recommend also "apt-get install exuberant-ctags",
then in each top-level directory where you work from, run "ctags -R".
you can then jump to any definition of any variable, class or
function, by putting the cursor on it and pressing "Ctrl-]"


> 2. Is this SoC in any way similar to the Xilinx ZYNQ architecture?.
> Where the ARM embedded processor would be replaced by PowerPC and the
> reconfigurable logic is converted to a GPU like entity, together forming a
> heterogeneous SoC.

ah no.  it *really is* an actual POWER9 core, where the plan is to
*extend* the POWER9 ISA (safely, and with careful mentoring from IBM
and the OpenPOWER Foundation), to add SimpleV vectorisation, YUV2RGB
instructions, Texture Interpolation instructions, and a shed-load
more.

those instructions *actually* run as *CPU* instructions, and we will
beef up the internal architecture to the point where it can cope with
the significant data and computational demands of executing GPU
workloads.  this is why we are going with a multi-issue OoO execution
engine, because it's the... "sane" way of dealing with the mixed
workloads of both sequential and parallel operations.

that is what being a "hybrid CPU-GPU-VPU" is all about.  it's very
much *not* about "farming off GPU workloads to elsewhere" - the
complete opposite is true.


> 3. Do you plan to run the SoC on an FPGA for prototyping and testing
> purposes?,

yes absolutely!  there is a EUR 10,000 budget allocated to this task:
https://bugs.libre-soc.org/show_bug.cgi?id=22

> or are you using some other methodologies?

i'd also like us to be able to use coriolis2 simulation.  this is
right at the gate level, about as close to the GDSII files as you can
get without actually paying for masks.

although it will be INSANELY slow, it will allow us to check that the
HDL has actually been properly translated into what we expect to be
executed.

l.

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Re: [libre-riscv-dev] Understanding the LibreSOC core

[Yehowshua]

> On Jun 8, 2020, at 2:24 PM, Luke Kenneth Casson Leighton <lkcl@lkcl.net> wrote:
> 
> yes absolutely!  there is a EUR 10,000 budget allocated to this task:
> https://bugs.libre-soc.org/show_bug.cgi?id=22 <https://bugs.libre-soc.org/show_bug.cgi?id=22>
Hey Luke! I totally forgot about this.
I should have my thesis done by end of June - crossing fingers.

I would like to work on that - popping LibreSOC ontop of LiteX and stuffing it
in my VersaECP5 - hope it fits - I’m a LiteX veteran at this point.
This would be at the beginning of July.

Can we get a gate count for this: http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-June/007828.html

Here’s to hoping its below 400k - otherwise - yeah…

Yehowshua
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Re: [libre-riscv-dev] Understanding the LibreSOC core

[Luke Kenneth Casson Leighton]

On Mon, Jun 8, 2020 at 7:46 PM Yehowshua <yimmanuel3@gatech.edu> wrote:
>
>
>
> > On Jun 8, 2020, at 2:24 PM, Luke Kenneth Casson Leighton <lkcl@lkcl.net> wrote:
> >
> > yes absolutely!  there is a EUR 10,000 budget allocated to this task:
> > https://bugs.libre-soc.org/show_bug.cgi?id=22 <https://bugs.libre-soc.org/show_bug.cgi?id=22>
> Hey Luke! I totally forgot about this.

:)

> I should have my thesis done by end of June - crossing fingers.
>
> I would like to work on that - popping LibreSOC ontop of LiteX

*great*.  by then that _should_ - as long as the wishbone interfaces
are up - be pretty straightforward to do.

> and stuffing it in my VersaECP5

oo i want one of those.

> - hope it fits - I’m a LiteX veteran at this point.

:)

> This would be at the beginning of July.
>
> Can we get a gate count for this: http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-June/007828.html
>
> Here’s to hoping its below 400k - otherwise - yeah…

ok so i ran the following yosys commands:

$ python soc/simple/core.py
$ yosys
read_ilang non_production_core.py
proc
opt
flatten
synth

and it produced this:

=== top ===

   Number of wires:              40844
   Number of wire bits:          93864
   Number of public wires:        5816
   Number of public wire bits:   58836
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:              42932
     $_ANDNOT_                   11780
     $_AND_                        399
     $_DFF_P_                     3542
     $_MUX_                      11446
     $_NAND_                      3272
     $_NOR_                        567
     $_NOT_                       2751
     $_ORNOT_                      419
     $_OR_                        8622
     $_XNOR_                        35
     $_XOR_                         99


> Yehowshua
> _______________________________________________
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Re: [libre-riscv-dev] Understanding the LibreSOC core

[Yehowshua]

Those look like reasonable numbers.

I think it should fit. At minimum, I can get it running
inside the LiteX Verilator environment.

Yehowshua

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Re: [libre-riscv-dev] Understanding the LibreSOC core

[Sanjay Menon]

Thanks for replying Luke.Would be looking into some of the things you
mentioned.

Yehowshua, if it does not fit you could try Partial dynamic reconfiguration
:)

Regards,
Sanjay

On Tue, 9 Jun 2020, 00:28 Yehowshua, <yimmanuel3@gatech.edu> wrote:

> Those look like reasonable numbers.
>
> I think it should fit. At minimum, I can get it running
> inside the LiteX Verilator environment.
>
> Yehowshua
>
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>
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Re: [libre-riscv-dev] Understanding the LibreSOC core

[Luke Kenneth Casson Leighton]

https://www.mouser.co.uk/ProductDetail/Lattice/LFE5UM-45F-VERSA-EVN?qs=J7VcZjJ3Z9cK61xZC6pcWg%3D%3D

is that the one?  LFE5UM-45F_VERSA-EVN?  it makes sense for me to get
one as well.

l.

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Re: [libre-riscv-dev] Understanding the LibreSOC core

[Yehowshua]

> 
> is that the one?  LFE5UM-45F_VERSA-EVN?  it makes sense for me to get
> one as well.

Yes - do hurry as there are only six left.
A fantastic alternative is the ulx3s.
The ulx3s uses SDR however, which LiTeX supports just fine.
The lead times of the ulx3s is two to three months however.
https://www.crowdsupply.com/radiona/ulx3s

> 
> l.
Yehowshua

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Re: [libre-riscv-dev] Understanding the LibreSOC core

[Yehowshua]

> 
> Yehowshua, if it does not fit you could try Partial dynamic reconfiguration

That is an interesting suggestion. Unfortunately, I’m pretty 
sure NextPnr does not support this at the moment.

https://github.com/YosysHQ/nextpnr

Yehowshua
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Re: [libre-riscv-dev] Understanding the LibreSOC core

[Yehowshua]

> On Jun 8, 2020, at 2:58 PM, Yehowshua <yimmanuel3@gatech.edu> wrote:
> 
> Those look like reasonable numbers.
> 
> I think it should fit. At minimum, I can get it running
> inside the LiteX Verilator environment.
> 

Also do keep in mind that LiteX **requires the CPU to 
initialize the DDR3 present on the Versa.

Two ways to approach this:
1. I can strip the LiteX BIOS down to bare essentials for initializing DDR3 on the Versa, and the build that.
Once built, I can comb through the assembled binary looking for any instructions we don’t 
currently support.
2. We can use SDR on the ulx3s which requires no CPU intervention.

Yehowshua


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Re: [libre-riscv-dev] Understanding the LibreSOC core

[Michael Nolan]

On 6/8/20 2:55 PM, Luke Kenneth Casson Leighton wrote:
>
> ok so i ran the following yosys commands:
>
> $ python soc/simple/core.py
> $ yosys
> read_ilang non_production_core.py
> proc
> opt
> flatten
> synth
>
> and it produced this:
>
> === top ===
>
>     Number of wires:              40844
>     Number of wire bits:          93864
>     Number of public wires:        5816
>     Number of public wire bits:   58836
>     Number of memories:               0
>     Number of memory bits:            0
>     Number of processes:              0
>     Number of cells:              42932
>       $_ANDNOT_                   11780
>       $_AND_                        399
>       $_DFF_P_                     3542
>       $_MUX_                      11446
>       $_NAND_                      3272
>       $_NOR_                        567
>       $_NOT_                       2751
>       $_ORNOT_                      419
>       $_OR_                        8622
>       $_XNOR_                        35
>       $_XOR_                         99

It should fit. Running synth_ecp5 instead of the generic asic synth 
above gives me this:

3.52. Printing statistics.

=== top ===

    Number of wires:              24216
    Number of wire bits:          72752
    Number of public wires:       24216
    Number of public wire bits:   72752
    Number of memories:               0
    Number of memory bits:            0
    Number of processes:              0
    Number of cells:              22710
      CCU2C                          72
      L6MUX21                      1203
      LUT4                        14962
      PFUMX                        3454
      TRELLIS_FF                   3019

--Michael


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Re: [libre-riscv-dev] Understanding the LibreSOC core

[Yehowshua]

> On Jun 8, 2020, at 4:11 PM, Michael Nolan <mtnolan2640@gmail.com> wrote:
> 
> LUT4                        14962

Yeah easily - we have an 85k LUT budget.
Awesome!

Yehowshua

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Re: [libre-riscv-dev] Understanding the LibreSOC core

[Luke Kenneth Casson Leighton]

On Mon, Jun 8, 2020 at 9:12 PM Yehowshua <yimmanuel3@gatech.edu> wrote:

> > On Jun 8, 2020, at 4:11 PM, Michael Nolan <mtnolan2640@gmail.com> wrote:
> >
> > LUT4                        14962

is that a lot?  i have no idea of "scale" if you know what i mean.
someone compiled microwatt for spartan-7 and got 11k LUTs
https://hackaday.com/2019/08/23/joining-the-risc-v-ranks-ibms-power-isa-to-become-free/

> Yeah easily - we have an 85k LUT budget.

the VersaECP5 from mouser is sadly only 45k LUTs, it does however have
the advantage of actually being available immediately.

> Awesome!

:)

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Re: [libre-riscv-dev] Understanding the LibreSOC core

[Luke Kenneth Casson Leighton]

On Mon, Jun 8, 2020 at 8:14 PM Yehowshua <yimmanuel3@gatech.edu> wrote:
>
>
>
> > On Jun 8, 2020, at 2:58 PM, Yehowshua <yimmanuel3@gatech.edu> wrote:
> >
> > Those look like reasonable numbers.
> >
> > I think it should fit. At minimum, I can get it running
> > inside the LiteX Verilator environment.
> >
>
> Also do keep in mind that LiteX **requires the CPU to
> initialize the DDR3 present on the Versa.

microwatt i believe did something like that (recently).

> Two ways to approach this:
> 1. I can strip the LiteX BIOS down to bare essentials for initializing DDR3 on the Versa, and then build that.

there's a BIOS??  oink :)

if there's a BIOS, it means that at least some instructions can be
loaded (into something - probably an on-board SRAM) and executed, and
that at least means we can test _something_ before getting to that
stage.

(meaning: the instructions to initialise DDR3 have to execute _from_
somewhere, they can't be executed from thin air)

btw we were planning to put in a "Board Support Package" NLNet Grant Request.

l.

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Re: [libre-riscv-dev] Understanding the LibreSOC core

[Luke Kenneth Casson Leighton]

https://github.com/enjoy-digital/litex/issues/245

okaaay, interesting.  later comments on that also explain some of the
commits i saw (changing xics)  overall it looks really exciting, and,
again, that they're trail-blazing for us.

l.

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Re: [libre-riscv-dev] Understanding the LibreSOC core

[Michael Nolan]

On 6/8/20 4:38 PM, Luke Kenneth Casson Leighton wrote:
> there's a BIOS??  oink :)
>
> if there's a BIOS, it means that at least some instructions can be
> loaded (into something - probably an on-board SRAM) and executed, and
> that at least means we can test _something_ before getting to that
> stage.
>
> (meaning: the instructions to initialise DDR3 have to execute _from_
> somewhere, they can't be executed from thin air)
>
> btw we were planning to put in a "Board Support Package" NLNet Grant Request.
>
We were going to need to do something like this anyway though, the 
actual SOC will need some low level boot code in rom right? For initial 
testing the 45f has 216kiB of bram, which is plenty for running test 
code and whatnot (granted, we will need some of that ram for other 
purposes).

--Michael


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Re: [libre-riscv-dev] Understanding the LibreSOC core

[Luke Kenneth Casson Leighton]

On Mon, Jun 8, 2020 at 10:19 PM Michael Nolan <mtnolan2640@gmail.com> wrote:
>
> On 6/8/20 4:38 PM, Luke Kenneth Casson Leighton wrote:
> > there's a BIOS??  oink :)
> >
> > if there's a BIOS, it means that at least some instructions can be
> > loaded (into something - probably an on-board SRAM) and executed, and
> > that at least means we can test _something_ before getting to that
> > stage.
> >
> > (meaning: the instructions to initialise DDR3 have to execute _from_
> > somewhere, they can't be executed from thin air)
> >
> > btw we were planning to put in a "Board Support Package" NLNet Grant Request.
> >
> We were going to need to do something like this anyway though, the
> actual SOC will need some low level boot code in rom right?

the original bugreport is basically for the hardware only
https://bugs.libre-soc.org/show_bug.cgi?id=22

as that milestone has been set and approved, if anyone does write any
low-level boot code, it can't come from that budget.  this is just how
it works.

> For initial
> testing the 45f has 216kiB of bram, which is plenty for running test
> code and whatnot

oh good.

> (granted, we will need some of that ram for other
> purposes).

L1 caches.  regfiles.

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Re: [libre-riscv-dev] Understanding the LibreSOC core

[Luke Kenneth Casson Leighton]

On Mon, Jun 8, 2020 at 11:17 PM Luke Kenneth Casson Leighton
<lkcl@lkcl.net> wrote:

> as that milestone has been set and approved, if anyone does write any
> low-level boot code, it can't come from that budget.  this is just how
> it works.

i could say "annoyingly", however i'm extremely grateful that NLNet
has provided some funding *at all*.

l.

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